FIG. 1 shows a conventional delay circuit. The first input of a two-input NAND gate 2 is connected to input terminal 1. Also, to the input terminal 1, a delay inverter (INV) 3 and a delay inverter 4 are connected in series. The second input of the NAND gate 2 is connected to the output of the delay inverter 4. An inverter 5 is connected to the output of the NAND gate 2, and the output of the inverter 5 is connected to output terminal 6. The delay inverter 3 and the delay inverter 4 have a same composition, and each of them is composed of a CMOS transistor (CMOS transistor) The delay inverter 3 is composed of a p-type MOSFET (p-channel transistor, hereinafter referred to as `PchTr`) 3a and a n-type MOSFET (n-channel transistor, hereinafter referred to as `NchTr`) 3b that are connected complementarily. The delay inverter 4 is composed of a PchTr 4a and a NchTr 4b that are connected complementarily.
In the composition shown in FIG.4, when there is no input signal IN, "H" level signal is applied to the input terminal 1. Signal input to the delay inverters 3, 4 side is inverted two times, therefore "H" level signals are input to both the inputs of the NAND gate 2. Thus, the output of the NAND gate 2 holds "L" level unalteredly. The output of the inverter 5 holds "H" level.
When input signal IN varies, i.e. a Low pulse generates, it is inverted at the inverter 3, thereby Low pulse part is changed into High pulse as well as providing a delay of t.sub.1 for the entire signal. This signal is further inverted and provided with a delay of t.sub.2 at the inverter 4, and is then applied to the second input of the NAND gate 2. The NAND gate 2 outputs "H" level signal unless both the input signals are "H" level. Namely, from a time point at the start edge (FALL) of input signal IN to a time point at the end edge (RISE) of output signal of the inverter 4, a "H" level signal is output from the NAND gate 2. This signal is inverted by the inverter 5 as well as being provided with a predetermined delay time. The output signal of the inverter 5 is output from the output terminal 6 as output signal OUT with end edge (RISE) delayed at the same mode (Low pulse) as the input signal IN.
Usually, in semiconductor devices, its pulse width, timing of various signals etc. are adjusted by a delay circuit. Even when the delay amount of delay circuit is dispersed due to a variation in process, the delay circuit can operate because it is designed provided with a margin in delay amount.
However, in the conventional delay circuit, when the operating frequency becomes as high as 100 to 200 MHz, due to the margin in delay amount, a desired performance is difficult to obtain and it is therefore necessary to enhance the precision. For example, a delay circuit used for a semiconductor memory uses pulse signal to pre-charge a digit line to be subject to the reading and writing. However, when trying to get such a pulse width that can be pre-charged certainly even under a condition that the pulse width becomes shortest, i.e. a condition that the gate length L shortens or the power-source voltage VDD increases, on the contrary, the operating speed of semiconductor memory is determined according to a condition that the pulse width becomes longest. Thus, a desired characteristic cannot be obtained.